1. Technical Field
This invention relates to data communication systems. More particularly, this invention relates high-speed communications systems including high-speed transmitters and receivers.
2. Description of Related Art
As electronic and computer technology continues to evolve, communication of information among different devices, either situated near by or at a distance becomes increasingly important. For example, it is now more desirable than ever to provide for high speed communications among different chips on a circuit board, different circuit boards in a system, and different systems with each other. It is also increasingly desirable to provide such communications at very high speeds, especially in view of the large amount of data required for data communications in intensive data consuming systems using graphical or video information, multiple input-output channels, local area networks, and the like.
It is particularly desirable to enable individual personal computers, workstations, or other computing devices, within which data is normally internally transferred using parallel data buses, to communicate with each other over relatively simple transmission lines. Such transmission lines typically include only one or two conductors, in contrast with the 64-bit and wider data paths within computing systems now commonly available.
A communication system that includes oversampling is often utilized to recover transmitted data. Such a system includes a receiver which samples the incoming serial data stream at a rate greater than the rate at which symbols (bits) are being transmitted. For example, in a three-times (3xc3x97) oversampling receiver, the incoming data stream is sampled at a rate approximately three times the symbol rate. However, there are various problems to overcome in order to effectively implement such a receiver when the rate of data transmission is very high. For example, parasitic capacitance and inductance typically introduce substantial distortion into the received signal.
The physical layer of the Gigabit Ethernet standard (IEEE 802.3z) requires a so-called PHY chip which operates at gigabaud speeds. Traditionally, either GaAs or bipolar techniques have been used to implement such PHY chips. However, GaAs and bipolar circuits cannot be easily integrated with other CMOS (complementary metal-oxide-semiconductor) circuits and are typically more costly to manufacture than CMOS circuits.
The above described needs are met and problems are solved by the present invention. New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.